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Embedded Vision Insights: November 5, 2019 Edition

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LETTER FROM THE EDITOR

Dear Colleague,Renesas webinar

Next Wednesday, November 13 at 10 am PT, Renesas Electronics America will deliver the free webinar "Renesas' Dynamically Reconfigurable Processor (DRP) Technology Enables a Hybrid Approach for Embedded Vision Solutions" in partnership with the Embedded Vision Alliance. DRP technology, built into select Arm Cortex-based RZ Family MPUs, accelerates image processing algorithms with runtime-reconfigurable hardware that delivers the acceleration benefits of dedicated circuitry while avoiding the cost and power penalties associated with embedded FPGA-based approaches. In this webinar, Renesas will explain the DRP architecture and its operation, present benchmarks and design examples demonstrating more than 10x the performance of traditional CPU-only solutions, and introduce resources for developing DRP-based embedded vision systems with the RZ/A2M MPU. For more information and to register, please see the event page.

One week later, Lattice Semiconductor will deliver the free webinar "Delivering Milliwatt AI to the Edge with Ultra-Low Power FPGAs," also in partnership with the Alliance. Low power FPGAs are well suited for implementing machine learning inferencing at the edge, given their inherent parallel architecture along with the ability to adapt to evolving deep learning algorithms and architectures. Lattice's iCE40 UltraPlus and ECP5 product families support development of edge AI solutions that consume from 1 mW to 1 W on compact hardware platforms. To accelerate development, Lattice has also brought...