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"Neural Network Compiler: Enabling Rapid Deployment of DNNs on Low-Cost, Low-Power Processors," a Presentation from Cadence

Megha Daga, Senior Technical Marketing Manager at Cadence, presents the "Neural Network Compiler: Enabling Rapid Deployment of DNNs on Low-Cost, Low-Power Processors" tutorial at the May 2018 Embedded Vision Summit.

The use of deep neural networks (DNNs) has accelerated in recent years, with DNNs making their way into diverse commercial products. But DNNs consume vast amounts of computation performance and memory bandwidth, creating challenges for developers seeking to deploy them in cost- and power-constrained systems. Specialized processors, such as the Cadence Tensilica Vision C5 DSP and Vision P6 DSP, address these performance and efficiency challenges. However, additional challenges arise due to time-to-market pressures, and from the complexities of DNN algorithms and specialized processor architectures.

Specialized software tools are key to addressing these challenges, enabling engineers to quickly generate efficient implementations of deep neural networks to run on specialized processors, without requiring detailed knowledge of the algorithms and processors. This talk illustrates how Cadence’s Neural Network Compiler enables engineers to start from a neural network description based on a framework such as TensorFlow or Caffe, and then quickly generate optimized fixed-point neural network code. Daga illustrates how the compiler speeds deployment from months to days. She also highlights compiler configurability options that help in optimizing system performance and shows how the generated code can be easily deployed to run in real time on an AI DSP hardware platform.