Bookmark and Share

General Discussion

The counterpart of GenICam for hardware interface?
4 replies [Last post]
zhenyu
zhenyu's picture
Offline
Last seen: 34 weeks 2 days ago
Level 3: Conjurer
Joined: 2011-06-01
Points: 45

The GenICam is gaining ground as a programming interface for cameras. It allows vision softwares to be portable among multiple types of camera interface, e.g. CameraLink, GigE Vision, etc.

However, there is no standard of hardware interface for cameras that allows third-party vision IPs to be portable to multiple types of camera interfaces. This is a big issue for FPGA-based vision systems. Due to the lack of such standard, the vision hardware IPs are coupled with the camera interface IP. Interchanging different types of camera interfaces, e.g. from CameraLink to GigE Vision, or even interchanging camera vendors, requires re-integration of the vision hardware IPs.

Many members in the Embedded Vision Alliance are producing FPGA-based product, e.g. Xilinx, AVNET, National Instruments, TED, etc. Wouldn't it be a good idea to initiate a hardware interface standard for cameras? Any comments are welcome.

Scott Gardner
Scott Gardner's picture
Offline
Last seen: 6 years 50 weeks ago
Level 9: Necromancer
Joined: 2011-02-09
Points: 366

Zhenyu,

You raise an excellent topic, since we're starting to discuss the logistics required to set standards through the Embedded Vision Alliance.  You describe the camera interface standard as a "hardware interface".  Are you suggesting a layered protocol that can work with different interface link technology -- like GenIcam's transport layer?  Perhaps you are suggesting that the EVA should help standardize on a single camera interface standard that already exists, but the market is fragmented by competing technologies.

I have my own opinions, but I'd like to see what others have to say in the discussion.

Folks, please post your thoughts.  This community is for you, and you have an opportunity to help set the direction for the industry.  There are several new technology providers joining the EVA, so this Forum is your chance to be heard by most of the players in the embedded vision industry.

Scott

zhenyu
zhenyu's picture
Offline
Last seen: 34 weeks 2 days ago
Level 3: Conjurer
Joined: 2011-06-01
Points: 45

Hello, Scott,

Sorry for the confusion from my previous post.

I think I can use pictures (in the attachment) to better explain the potential benefit of a new standard for embedded vision system, especially for FPGA-based embedded vision system.

The GenICam is providing a software API to abstract the camera and its interface.

However, embedded vision often involves image processing on hardware instead of software. Then the vision processing library are hardware designs, often from third-party. A new standard is required to provide a portable hardware interface between hardware vision library and different types of cameras and interfaces.

Zhenyu

AttachmentSize
GenICam standard 142.94 KB
New standard is required for FPGA based vision system 124.72 KB
Scott Gardner
Scott Gardner's picture
Offline
Last seen: 6 years 50 weeks ago
Level 9: Necromancer
Joined: 2011-02-09
Points: 366

zhenyu wrote:

However, embedded vision often involves image processing on hardware instead of software. Then the vision processing library are hardware designs, often from third-party. A new standard is required to provide a portable hardware interface between hardware vision library and different types of cameras and interfaces.

Zhenyu,

Thanks for clarifying this with a picture.  I had looked at the GenICam spec, and it seemed like a good solution already.  Now, I believe I understand you better when you say that hardware designs are more difficult to design with this software focus on abstraction.  I still think that any standard will have to support some sort of layered protocol, but I can see where the existing standard could get in the way.

The good news is that Xilinx is really interested in Embedded Vision, and we can just ask their guys to comment.  If you haven't already seen it, you might want to watch Jeff's conversation with Jose Alvarez -- the key guy at Xilinx who runs their library group.  He'll be able to answer this question about the commonality for interface IP in their library and how it bolts into the system with your custom algorithms.  I imagine that most of these blocks use a standardized header for memory-mapped peripherals, since that is how they describe the library functions for the forthcoming Zynq EPP (ARM-based).  Hopefully they can just comment in your Forum thread.

Thanks for bringing this up.  The topic is timely...

zhenyu
zhenyu's picture
Offline
Last seen: 34 weeks 2 days ago
Level 3: Conjurer
Joined: 2011-06-01
Points: 45

Hello, Scott,

Thanks for the pointer to the video. Let's wait and see whether xilinx or other members of EVA are interested in making such standard.

In case Xilinx is also reading this thread, I have one additional comment. From the applicatiosn we had analysed with our industrial partners, the data path of a general purposed  processor on the FPGA, no matter it is microblaze or powerpc or arm, can not handle the bandwidth requirement of front-end image processing. It is not feasible to use a processor on the FPGA, let alone a software driver, to interface with the industrial camera. In most industrial applicatioms, hardware IP is the only option for front-end image processing. Therefore, we need a standard interface between front-end processing hardware IP and the camera.