October 2013 Embedded Vision Summit Technical Presentation: "Designing a Multi-Core Architecture Tailored for Pedestrian Detection Algorithms," Tom Michiels, Synopsys
Tom Michiels, R&D Manager at Synopsys, presents the "Designing a Multi-Core Architecture Tailored for Pedestrian Detection Algorithms" tutorial within the "Algorithms and Implementations" technical session at the October 2013 Embedded Vision Summit East.
Pedestrian detection is an important function in a wide range of applications, including automotive safety systems, mobile applications, and industrial automation. A popular algorithm for pedestrian detection is HOG (Histogram of Oriented Gradients). Several variants of the algorithm have been proposed. The complexity and diversity of these algorithms demands a programmable implementation. Michiels compares the suitability of different embedded processor architectures to implement the HOG algorithm, with a focus on performance and power consumption. He covers MCUs, DSPs, and embedded GPUs.
Looking beyond standard processor architectures, he discusses the advantages that can be achieved by tailoring an architecture to the specific requirements of the application, in the case of HOG resulting in a heterogeneous multi-core solution. In contrast to choosing among standard processors, building a tailored multi-core solution is a design task. He explains the methodology Synopsys applied to partition the algorithm and map it to heterogeneous special-purpose processor cores. He discusses how to parallelize the design process among a team of algorithm, hardware and software engineers; the role of a virtual prototype; and the need for an FPGA-based prototyping system.